A common mode feedback (CMFB) loop is required to maintain the desired common mode voltage level on the output of a differential charge pump. A conventional CMFB circuit adjusts the magnitude of the output source versus sink current in order to find the correct common mode balance. In a PLL based synthesizer the charge pump output is only active for a fraction of a reference cycle, e.g. for 1 ns out of 40 ns, in order to minimize noise from the charge pump. Single ended charge pump and loop filter structures are used in conventional PLL synthesizers and so do not require CMFB. However, they suffer from relatively poor up/down charge pump mismatch which gives rise to static phase errors at the PFD inputs and cause reference spur sidebands on the PLL output spectrum.
An improved PLL synthesizer can be made with a differential charge pump, for improved up/down mismatch, and narrow output pulses, for lowest noise. A CMFB loop would be required though. Narrow charge pump output pulses are problematic with a conventional CMFB loop. Since it adjusts the magnitude of the output currents, it may need to make excessively large current (and hence PLL loop gain) changes to counter parasitic effects, such as charge injection, which may be of similar magnitude to the charge delivered by the narrow output current pulses. A change in loop gain can cause changes in loop dynamics resulting in less than optimum lock times and even instability.